analog w devices high resolution 14-bit sample and hold amplifier features :t10v min input/output range 50ns aperture delay 0.5ns aperture jitter -a ",;.r/.h';' 6p~time ~ -r :to.001% max gain linearity error complete with input buffer applica tlons track and hold peak measurement systems data acquisition systems simultaneous sample-and-hold general description the shal144 is a fast sample-hold amplifier module with ac curacy and dynamic performance appropriate for applications with fast 14-bit aid converters. in the "sample" mode, it acts as a fast amplifier, tracking the input signal. when switched to the "hold" mode, the output is held at a level corresponding to the input signal voltage at the instant of switching. the droop rate in "hold" is appropriate to allow accurate conver- sion by 14-bit aid converters having conversion times of up to 150ps. dynamic performance the sha1144 was designed to be compatible with fast 14-bit aid converters such as the analog devices' adcl130 and adc1131 series, which convert 14 bits in 25/1s and 12/1s, re- spectively. maximum acquisition time of 8ps for the sha1144 permits high sampling rates for 14-bit conversions. the shal144 is guaranteed to have a maximum gain nonlinearity of :to.ool % of full scale to insure 1/2lsb accuracy in 14-bit systems. when in the "hold" mode, the droop rate is 1pv/ps, so the sha1144 will hold an input signal to :to.oo3% of full scale (20v pop) for over 600ps. principle of operation the shal144 consists basically of two high speed operational amplifiers, a storage capacitor, and a digitally controlled switch. it differs from typical sample-and-hold modules in one important respect; application versatility. the user completes the shal144 feedback circuit external to the module. there- fore, the module may be used in inverting or noninverting con- figurations and can easily be arranged to provide circuit gain of more than unity to simplify signal conditioning in a subsystem. information furnished by analog devices is believed to be accurate and reliable. however. no responsibility is assumed by analog devices for its use; nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implica- tion or otherwise under any patent or patent rights of analog devices. \j specifications @+25c, gain = +1viv and nominal unless otherwise noted) model accuracy gain gain error gain nonlinearity gain temperature coefficient (0 to +70c) input characteristics input voltage range impedance bias current initial offset voltage offset vs. temperature (0 to +70c) output characteristics voltage current resistance capacitive load noise @ 100khz bandwidth 1mhz bandwidth sample mode dynamics frequency response small signal (-3db) full power slew rate --._---- sha1144 +lv/v :to.005% :to.0005% (:to.001 % max) :t1ppm/c (:t2ppm/c max) :t10v loll n 1l1opf 0.5na max adjustable to zero :t30ilv/c max :t10v min :t20ma min (- figure 2 shows feedback connections to the sha1144 for the unity gain follower mode. output (pin 9) is connected to in- put (pin 4). input signal is applied to pin 3. +input figure 2. unity gain follower ( figure 3 shows feedback connections for noninverting op- eration with potentiometric gain. when the indicated values are installed, gain will be +5. as in all operational amplifiers, gain-bandwidth product is a constant for a given sample-and- hold. effective 3db bandwidth will be inversely proportional to gain. r1 1k +15v r2 4k +input output -15v (" figure 3. noninverting operation by using conventional operational amplifier feedback con- nections, the sha1144 can be connected for use as an inverter, with various gains (as determined by the rf/ri ratio), or as a differential amplifier. da t a acquisition application successive-approximation aid converters can generate substan- tiallinearity errors if the analog input varies during the period of conversion; even the fast 14-bit models available cannot tolerate input signal frequencies of greater than a few hz. for this reason, sample-and-hold amplifiers like the sha1144 are connected between the aid and its signal source to hold the analog input constant during conversion. when the sha1144 is connected to an aid, its aperture time uncertainty, rather than the aid's conversion time, is the fac- tor which limits the allowable input signal frequency. the sha1144, with a typical aperture delay time of 50ns and an uncertainty of 0.5ns, will change from the sample mode to the hold mode 50 to 50.5ns after the" 1" to "0" transition of the mode control input. if the system timing is so arranged as to initiate the mode control signal 50ns early, then switching will actually occur within 0.5ns of the desired time as shown below. v analog input/output signals - sha input signal -- sha output signal i sha1144 mooe ;/"///~sample 'l///~ hold~~ ~---, i i--- 50ns i ~ desired switching point sha1144 mode control input figure 4. aperture uncertainty the maximum allowable slew rate will thus equal the quotient of the maximum allowable voltage uncertainty and the 0.5ns aperture uncertainty. for sinewave inputs, the corresponding maximum frequency is expressed by: fmax = (i1e ) (--1-) ==3.18xl08 (i1e ) efs 2nl1t efs where: i1e = the allowable voltage uncertainty efs = the sinewave magnitude for a system containing a sha1144 and a 14-bit aid with :tl0v input signals and an allowable input uncertainty of :tl/2lsb (:t620ilv), the maximum allowable signal frequen- cy will be 19.7khz. power supply and grounding connections the proper power supply and grounding connections are shown shown below in figure 5. '15v +5v 902-2 905 +15v com -15v com +5v to digital logic 7 analog gnd 10"f 35v 1+ sha1144 -15v lo"f ,+35v 6 +15v 11 dig gnd figure 5. power supply and grounding connections the :t15v power supplies must be externally bypassed as shown. the capacitors should be tantalum types and should be installed as close to the module pins as possible. the analog and digital ground lines should be run separately to their respective power supply commons to prevent coupling of digital switching noise to the sensitive analog circuit section. -3- - obsolete
operation with an aid converter figure 6 below shows the appropriate connections between the sha1144 and a successive approximation aid converter in block diagram form. operation with an aid and multiplexer the subsystem of figure 9 may also be connected to a multi- plexer like the harris hi508a as shown below. convert command input itaytjs status sha1144 input input output mode control convert j1... command figure 6. sha 1144 and aid connections the resulting timing sequence at the start of conversion is illus- trated in figure 7, sha1144 input output signals ~"""'/~i-------- ----- sha1144 mode /ii --n i '/ sample ~ """"""""""""'\;' h'o'ld ~""""""""""""""""'\; ii i j i f --j r ap:r~re dela y ~ 50n' switching transient settling ~ 1", -- input - output convert 1 command 0 status output! 1 ~n~~~ control 0 figure 7. aid and sha timing at start of conversion 1 note that the leading edge of the convert command pulse causes the converter's status output to go to logic "0" which in turn switches the sha1144 from sample to hold. as discussed previously, the typical sha1144 actually changes modes 50 to 50.5ns after the "1" to "0" transition of the mode control input. this mode switching causes a transient on the output terminal which decays to within 0.003% of the final value in approximately ills, once the transient has settled, the convert command input is returned to logic "0" and the conversion proceeds. as shown in figure 8, the status signal returns to logic "1" and the sha1144 returns to the sample mode at the end of conversion. within 611s, it will have acquired the input signal to 0.003% accuracy and a new conversion cycle may be started. sha1144 input! output signals -- input - output sha1144 mode i 1 1 i i '" e ' //'//////ffi ' '/'////, sampl 0:: hold \:w/, ~ l _i acquisition [i time~6"s f 'n. :d status output! 1 mode control input 0 ~ figure 8. aid and sha timing at end of conversion ! digital output hi50sa shal144 a/d converter output input output input mode control figure 9. aid, sha, and mpx connections the leading edge of the convert command pulse sets the status output to logic "0" thereby switching the sha1144 to "hold"; the corresponding change to logic" 1" of the status output increments the binary counter and changes the multiplexer address. since the sha1144's aperture time is small with respect to the multiplexer switching time, it will have switched to the hold mode before the multiplexer actu- ally changes channels. the multiplexer switching transients will settle out long before the sha returns to "sample" at the end of conversion. the timing sequence described above is illustrated in figure 10. multiplexer output! sha input +10v r= ov -10v hw !~"~'e:' "'" ~'e:';"'" ~,~"'~ ~" .:' l f . f \to sha1'44 mode sha output/ aid input channel being digitized channel 1 - channel 2 - channel 3 - figure 10. aid, sha, and mpx timing this method of sequencing the multiplexer may be altered to permit random addressing or addressing in a preset pattern. the timing of the multiplexer address changes may also be altered but consideration should be given to the effects of feed through in the sha1144. feedthrough is the coupling of analog input signals to the output terminal while the sha is in "hold". large multiplexer switching transients occuring during aid conversion may introduce an error. -4- ""0 e} channel "nput to : digital i input converter digital i i output i i convert i i status command i channel s input convert ----il n n command a;eug;:t'nput ---, n n r mul tlplexer ch" +8v i i i channel ch2, -10v ch 3, +3v ch4, ov obsolete
general description high resolution, high speed data acquisition demands that con- siderable thought be given to wiring connections, even when simply evaluating the unit in a temporary laboratory bench set-up. to assist with such evaluations, an ac1580 is available. this 4 1/2" x 6" printed circuit card has sockets that allow a sha1144 and adcl130 or adcl131 to be plugged directly onto it. it also has provisions for two optional harris hi508a multiplexers. this card includes gain and offset adjustment potentiometers and power supply bypass capacitors. it mates with a cinch 251-22-30-160 (or equivalent) edge connector (po and cinch 251-06-30-160 (or equivalent) edge connector (p2) which are supplied with every card. to use the ac1580, program as shown in the wiring chart of table 1, by installing the appropriate jumpers. an ou tline drawing and schematic are provided for reference. calibration procedure set up the sha1144 for the desired gain per the wiring chart of table 1. short w9 which drives the sha mode control with the status of the adc. calibrate offset and gain in the manner described below. when calibration is completed w9 ~~~~~ u status y bit 141lsbi 3 bit 13 2 bit 12 n bit 11 m bit 10 l bit 9 k bit b j bit 7 h bit 6 f bit 5 e i~ 61 23 bit 1 (msbi k bit 4 0 bit 3 c msb 1 bit 2 b i wl0 : +15v add~~s~ 1 add~e~~ 2 add~e~~ 3 add~~s~ 4 p2 i i i" i i i i ~z i i 15 4 5 6 '111 7 ihi50bai 12 11 10 9 16 16 8 4 5 6 s2 7 (hi50ba) 12 11 10 9 15 3 14 13 -15v - +15v -15v may be removed and the sha mode cont~ol may be driv- en in accordance with the option chart. offset calibration for the 0 to +10v unipolar range set the input voltage pre- cisely to +0.0003v. adjust the zero potentiometer until the converter is just on the verge of switching from 00. . . . . 0 to 00.. . . . 1. for the +5v bipolar range, set the input voltage precisely to -4.9997v: for :t10v units set it to -9.9994v. adjust the zero potentiometer until offset binary coded units are just on the verge of switching from 00 . . . . . 0 to 00 . . . . . 1 and two's complement coded units are just on the verge of switching from100 0to100 1. gain calibration set the input voltage precisely to +9.9991v for 0 to +10v units, +4.9991v for :t5v units or +9.9982v for :t10v units. note that these values are 1 1i2lsb's less than the nominal full scale. adjust the gain potentiometer until binary and off- set binary coded units are just on the verge of switching from 11 . . . . 0 to 11 . . . . 1 and two's complement coded units are just on the verge of switching from 011 . . . 10 to 011 . . . 11. pl i r clock output p clock input v convert command z status s serial output i - 15 digital gnd t +5v 17 +15v ! w9 16 -15v 20 gnd sense rw3 .-'v"v-, pl i 11 digital 15 gnd w8 i mode mo-r-o 9 control i i 4- 10 m2 sha1144 9 8 16 -15v 17 +15v 2 1 w7 +15v r3 look offset p2 w12,0 : 06 analog input -0' w15' :=wj: 5 analog gnd w13 pi -<>~' : 18 analog input w14 '0 i 019 analog gnd w16 p2 i a inch 1 b in ch 2 c in ch 3 0 in ch 4 e in ch 5 f in ch 6 h in ch 7 j in ch b k in ch 9 l in ch 10 minch 11 n in ch 12 9 in ch 13 10 in ch 14 11 in ch 16 12 in ch 16 figure 11. schematic and pin designations -5- pl i. 36 37 i 43 35 :w6 i 44 34 i 46 33 4b 32 i 50 30 52 29 m1 i 54 adc1130/1131 27 i 56 125 obsolete
outline dimensions dimensions shown in inches and (mm). 45(114.3( l 295(74.921 2.02/51.31 w3 w4 i ! i w7 w13! of ~ fset u gain w14: 0 1 0 g 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 q ._0 6.0 1152.41 i' w12: !w2 w15' iw1 w51 0 (]i mjl2 0" wll---wlo w61 !w9 w16 c4d go of .vj~- a r-j li--~ l l--j~ 3575(9081 >-1 ?i~6~1: : ij:: ~::jmtt:::(m[mtjtt:umt[r---~~ notes ,. p1 is cinch connector type 251.22.30.160. 2. p21s cinch connector type 251.1)6.30.160 figure 12. ac1580mounting board -- a to d converter options range jumpers ov to iov :!:5v :!:iov jumper wii jumper wll and jumper g to f on board jumper wio and jumper g to f on board sha unity gain (+ 1) sha with gainl,3 sha options jumper wi and jumper w7 jumper wi and install rw4 and rw7 in w4 and w7 locations3 jumper w2 and jumper w5 and install rw3 and rw7 in w3 and w7 locations3 0 co en i 0 'i '" ~ ~ i!) u sha as an inverter2,3 sha mode control internal (driven from status of the adc) external (apply external signal to pin 9 of connector pi) jumper w9 jumper w8 multiplexer option when using multiplexers jumper wi6 input options inputs analog input analog ground from connector pi from connector p2 jumperwi5 jumperwi2 ju,mper wl4 jumper w13 notes 'g~l+ rw7 2g~- rw7 rw4 rw3 3 see figure 11 for appropriate gain setting resistor locations (rw3, rw4, rw7) table 1. option chart ) <1: 0 :j z 0 lu ~ z ex: a.. -6- "on" channell 2 3 4 1 l l l l l = ttl logic "0" 2 l l h l (ov?"o" ?+0.8v) 3 l h l l 4 l h h l h=ttl logic "i" 5 h l l l (+2v?"i"?+5.5v) 6 h l h l 7 h h l l 8 h h h l 9 l l l h 10 l l h h 11 l h l h 12 l h h h 13 h l l h 14 h l h h 15 h h l h 16 h h h h table 2. multiplexer address obsolete
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